ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

C5.5 Privilege in Debug state
Debug State
In Debug state, instructions issued to the processor have the privileges to access and modify processor
registers, memory and coprocessor registers that they would have if issued in the same mode and security
state in Non-debug state.
In User mode and Debug state, instructions have additional privileges to access or modify some registers
and fields that cannot be accessed in User mode in Non-debug state. However, on processors that implement
the Security Extensions and support Secure User halting debug, these additional privileges are restricted
when all the following conditions are true:
the processor is in Debug state
the processor is in Secure User mode
invasive debug is not permitted in Secure privileged modes, because either DBGEN or SPIDEN is
LOW, see Chapter C2 Invasive Debug Authentication.
The following sections describe the instruction privileges, and the restrictions on them when these
conditions are all true:
Accessing registers and memory in Debug state
Altering CPSR privileged bits in Debug state on page C5-14
Changing the SCR.NS bit in Debug state on page C5-15
Coprocessor and Advanced SIMD instructions in Debug state on page C5-16.
C5.5.1 Accessing registers and memory in Debug state
The rules for accessing ARM core registers and memory are the same in Debug state as in Non-debug state.
For example, if the CPSR mode bits indicate the processor is in Supervisor mode:
reads of ARM core registers return the Supervisor mode registers
normal load and store operations make privileged accesses to memory
a load or store with User mode privilege operation, for example LDRT, makes a User mode privilege
access.
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