ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The System Level Programmers’ Model
Note
All hardware ID information can be accessed only from privileged modes.
The FPSID is privileged access only.
This is a change in VFPv3. In VFPv2 implementations the FPSID register can be accessed
in all modes.
The MVFR registers are privileged access only.
User code must issue a system call to determine what features are supported.
B1.8.3 The Floating-Point Exception Register (FPEXC)
The Floating-Point Exception Register (FPEXC) provides global enable and disable control of the
Advanced SIMD and VFP extensions, and to indicate how the state of these extensions is recorded.
The FPEXC:
Is in the CP10 and CP11 register space.
Is present only when at least one of the VFP and Advanced SIMD extensions is implemented.
Is a 32-bit read/write register, that can have different access rights for different bits.
If the Security Extensions are implemented, is a Configurable access register. The FPEXC is only
accessible in the Non-secure state if the CP10 and CP11 bits in the NSACR are set to 1, see c1,
Non-Secure Access Control Register (NSACR) on page B3-110
Is accessible only in privileged modes, and only if access to coprocessors CP10 and CP11 is enabled
in the Coprocessor Access Control Register, see:
— c1, Coprocessor Access Control Register (CPACR) on page B3-104 for a VMSA
implementation
— c1, Coprocessor Access Control Register (CPACR) on page B4-51 for a PMSA
implementation.
Has a reset value of 0 for bit [30], FPEXC.EN.
The format of the FPEXC is:
31 30 29 0
EXEN SUBARCHITECTURE DEFINED
EX, bit [31] Exception bit. A status bit that specifies how much information must be saved to record the
state of the Advanced SIMD and VFP system:
0 The only significant state is the contents of the registers:
D0 - D15
D16 - D31, if implemented
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