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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Debug Register Interfaces<br />

C6.1 About the debug register interfaces<br />

The Debug architecture defines a set of debug registers. The debug register interfaces provide access to these<br />

registers. This chapter describes the different ways of implementing the debug register interfaces.<br />

The debug register interfaces provide access to the debug registers from:<br />

software running on the processor, see Processor interface to the debug registers<br />

an external debugger, see External interface to the debug registers.<br />

The debug register interfaces always include the Debug Communications Channel, see The Debug<br />

Communications Channel (DCC) on page C6-3.<br />

C6.1.1 Processor interface to the debug registers<br />

Table C6-4 on page C6-32 lists the set of CP14 debug instructions for accessing the debug registers that<br />

must be implemented.<br />

The possible interfaces between the software running on the processor <strong>and</strong> the debug registers are:<br />

The Baseline CP14 interface. This provides access to a small set of the debug registers through a set<br />

of coprocessor instructions. It must be implemented by all processors.<br />

The Extended CP14 interface. This provides access to the remaining debug registers through a<br />

coprocessor interface. It is required in v6 Debug <strong>and</strong> v6.1 Debug, <strong>and</strong> is optional in v7 Debug.<br />

The memory-mapped interface. This provides memory-mapped access to the debug registers. It is<br />

introduced in v7 Debug, <strong>and</strong> is an optional interface. When it is implemented:<br />

— some of the registers that are accessed through the Baseline CP14 interface are not available<br />

through the memory-mapped interface<br />

— it is IMPLEMENTATION DEFINED whether the memory-mapped interface is visible only to the<br />

processor in which the debug registers are implemented, or is also visible to other processors<br />

in the system.<br />

An <strong>ARM</strong>v7 implementation must include the Baseline CP14 interface <strong>and</strong> at least one of:<br />

the Extended CP14 interface<br />

the memory-mapped interface.<br />

C6.1.2 External interface to the debug registers<br />

Every <strong>ARM</strong>v6 <strong>and</strong> <strong>ARM</strong>v7 implementation must include an external debug interface. This interface<br />

provides access to the debug registers from an external debugger through a Debug Access Port (DAP). This<br />

interface is IMPLEMENTATION DEFINED. For details of the interface recommended by <strong>ARM</strong>:<br />

for an <strong>ARM</strong>v7 implementation, see the <strong>ARM</strong> Debug Interface v5 <strong>Architecture</strong> Specification<br />

for an <strong>ARM</strong>v6 implementation, contact <strong>ARM</strong>.<br />

C6-2 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

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