ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

If the Security Extensions are implemented
Debug Events
The Secure Local and Non-secure Local vector addresses for IRQ and FIQ vector catch are
determined by the appropriate banked copy of the SCTRL.VE bit:
If the SCTRL.VE bit is set to 0, then the corresponding Local vector addresses for
IRQ and FIQ vector catch are determined by the banked exception base address.
If the SCTRL.VE bit is set to 1, then for each of IRQ and FIQ vector catch:
— if the interrupt is taken in Secure or Non-Secure IRQ mode or FIQ mode, then
the corresponding Local vector address is the interrupt vector address supplied
by the interrupt controller on taking the interrupt.
— if the interrupt is taken in Monitor mode, then it is IMPLEMENTATION DEFINED
whether the IRQ and FIQ Vector Catch debug events generated from the Local
vector addresses can occur, and if they can occur the Secure and Non-secure
Local vector addresses for the vector catches are IMPLEMENTATION DEFINED.
The Monitor vector addresses for IRQ and FIQ vector catch are determined by the Monitor
exception base address.
When the Vector Catch debug logic uses addresses supplied by the interrupt controller, then:
if the interrupt controller has not supplied an interrupt address to the processor since vectored
interrupt support was enabled then no Vector Catch debug events using Local vector addresses are
generated
if Vector Catch debug events were not enabled when the interrupt controller supplied a vector address
to the processor, but have been enabled since, an implementation must consistently either:
— generate a Vector Catch debug event if the IVA of an instruction matches the Local vector
address
— not generate Vector Catch debug events using any Local vector address.
C3.2.5 Memory addresses
On processors that implement the Virtual Memory System Architecture (VMSA), and also implement the
Fast Context Switch Extension (FCSE):
It is IMPLEMENTATION DEFINED whether the Instruction Virtual Address (IVA) used in generating
Breakpoint debug events is the Modified Virtual Address (MVA) or Virtual Address (VA) of the
instruction.
It is IMPLEMENTATION DEFINED whether the Data Virtual Address (DVA) used in generating
Watchpoint debug events is the MVA or VA of the data access.
The IVA used in generating Vector Catch debug events is always the VA of the instruction.
The Watchpoint Fault Address Register (DBGWFAR) reads a VA plus an offset that depends on the
processor instruction set state.
The Program Counter Sampling Register (DBGPCSR), if implemented, reads a VA plus an offset that
depends on the processor instruction set state.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C3-23