ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Register Interfaces
C6.5 Access permissions
This section describes the basic concepts of the access permissions model for debug registers on ARMv7
processors. The actual rules for each interface, and for ARMv6 implementations, are given in the section
describing the register interface:
CP14 debug registers access permissions on page C6-36
Permission summaries for memory-mapped and external debug interfaces on page C6-45.
The restrictions for accessing the registers can be divided into three categories:
Privilege of the access
Accesses from processors in the system to the memory-mapped registers, and accesses to
coprocessor registers, can be required to be privileged.
Locks Can be used to lock out different parts of the register map so they cannot be accessed.
Power-down Access to registers in the core power domain is not possible when that domain is powered
down.
When permission to access a register is not granted, an error is returned. The nature of this error depends on
the interface:
For coprocessor interfaces, the error is an Undefined Instruction exception
For the memory-mapped interface, the error is a slave-generated error response, for example
PSLVERRDBG. The error is normally signaled to the processor as an external abort.
For the external debug interface, the error is signaled to the debugger by the Debug Access Port.
Holding the processor in warm reset, whether by using an external warm reset signal or by using the Device
Power-down and Reset Control Register (DBGPRCR), does not affect the behavior of the memory-mapped
or external debug interface.
The Hold non-debug reset control bit of the DBGPRCR enables an external debugger to keep the processor
in warm reset while programming other debug registers. For details see Device Power-down and Reset
Control Register (DBGPRCR), v7 Debug only on page C10-31.
C6.5.1 Permissions in relation to the privilege of the access
The majority of debug registers can only be accessed by privileged code. The exception to this general
requirement is a small subset of the registers, defined in The Baseline CP14 debug register interface on
page C6-32. Using the coprocessor interface, privileged code can disable User mode access to this subset of
registers.
For the memory-mapped interface, it is IMPLEMENTATION DEFINED whether restricting debug register access
to privileged code is implemented by the processor or must be implemented by the system designer at the
system level. The behavior of an access that is not permitted is IMPLEMENTATION DEFINED, however it must
either be ignored or aborted.
C6-26 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B