ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

c0, Cache Type Register (CTR)
ARMv4 and ARMv5 Differences
The format of the Cache Type Register is significantly different from the ARMv7 definition described in c0,
Cache Type Register (CTR) on page B3-83. However, the general properties described by the register, and
the access rights for the register, are unchanged.
This section describes the implementation of the CP15 c0 Cache Type Register and is applicable to a VMSA
or PMSA implementation.
The Cache Type Register supplies the following details about the level 1 cache implementation:
whether there is a unified cache or separate instruction and data caches
the cache size, line length, and associativity
whether it is a Write-Through cache or a Write-Back cache
the cache cleaning and lockdown capabilities.
The format of the Cache Type Register is:
31 29 28 25 24 23 12 11 0
0 0 0 Ctype S DSize ISize
Ctype, bits [28:25]
Cache type field. Specifies details of the cache not indicated by the S bit and the Dsize and
Isize fields. Table H-13 shows the encoding of this field. All values not specified in the table
are reserved.
S, bit [24] Separate caches bit. The meaning of this bit is:
0 Unified cache
1 Separate instruction and data caches.
If S == 0, the Isize and Dsize fields both describe the unified cache, and must be identical.
Dsize, bits [23:12]
Specifies the size, line length and associativity of the data cache, or of the unified cache if
S == 0. For details of the encoding see Cache size fields on page AppxH-36.
Isize, bits [11:0]
Specifies the size, line length and associativity of the instruction cache, or of the unified
cache if S == 0. For details of the encoding see Cache size fields on page AppxH-36.
Table H-13 shows the Ctype values that can be used in the CTR:
Table H-13 Cache type values
Ctype a Cache method Cache lockdown b
0b0000 Write-Through Not supported
0b0010 Write-Back Not supported
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxH-35