ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
B3.12.10 c0, TLB Type Register (TLBTR)
The TLB Type Register, TLBTR, provides information about the TLB implementation. The register must
define whether the implementation provides separate instruction and data TLBs, or a unified TLB.
Normally, the IMPLEMENTATION DEFINED information in this register includes the number of lockable
entries in the TLB.
The TLBTR is:
a 32-bit read-only register
accessible only in privileged modes
implemented only when the VMSA is implemented
when the Security Extensions are implemented, a Common register.
The format of the TLBTR is:
31 1 0
Bits [31:1] IMPLEMENTATION DEFINED.
nU, bit [0] Not Unified TLB. Indicates whether the implementation has a unified TLB:
nU == 0 Unified TLB.
nU == 1 Separate Instruction and Data TLBs.
Note
From ARMv7, the TLB lockdown mechanism is IMPLEMENTATION DEFINED, and therefore the details of
bits [31:1] of the TLB Type Register are IMPLEMENTATION DEFINED.
Accessing the TLBTR
To access the TLBTR you read the CP15 registers with set to 0, set to c0, set to c0, and
set to 3. For example:
MRC p15,0,,c0,c0,3 ; Read CP15 TLB Type Register
IMPLEMENTATION DEFINED nU
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