ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

A3.4.6 Semaphores
Application Level Memory Model
The Swap (SWP) and Swap Byte (SWPB) instructions must be used with care to ensure that expected behavior
is observed. Two examples are as follows:
1. A system with multiple bus masters that uses Swap instructions to implement semaphores that control
interactions between different bus masters.
In this case, the semaphores must be placed in an uncached region of memory, where any buffering
of writes occurs at a point common to all bus masters using the mechanism. The Swap instruction
then causes a locked read-write bus transaction.
2. A systems with multiple threads running on a uniprocessor that uses the Swap instructions to
implement semaphores that control interaction of the threads.
In this case, the semaphores can be placed in a cached region of memory, and a locked read-write bus
transaction might or might not occur. The Swap and Swap Byte instructions are likely to have better
performance on such a system than they do on a system with multiple bus masters such as that
described in example 1.
Note
From ARMv6, use of the Swap and Swap Byte instructions is deprecated. All new software should use the
Load-Exclusive and Store-Exclusive synchronization primitives described in Synchronization and
semaphores on page A3-12, for example LDREX and STREX.
A3.4.7 Synchronization primitives and the memory order model
The synchronization primitives follow the memory order model of the memory type accessed by the
instructions. For this reason:
Portable code for claiming a spin-lock must include a Data Memory Barrier (DMB) operation,
performed by a DMB instruction, between claiming the spin-lock and making any access that makes
use of the spin-lock.
Portable code for releasing a spin-lock must include a DMB instruction before writing to clear the
spin-lock.
This requirement applies to code using:
the Load-Exclusive/Store-Exclusive instruction pairs, for example LDREX/STREX
the deprecated synchronization primitives, SWP/SWPB.
A3.4.8 Use of WFE and SEV instructions by spin-locks
ARMv7 and ARMv6K provide Wait For Event and Send Event instructions, WFE and SEV, that can assist with
reducing power consumption and bus contention caused by processors repeatedly attempting to obtain a
spin-lock. These instructions can be used at application level, but a complete understanding of what they do
depends on system-level understanding of exceptions. They are described in Wait For Event and Send Event
on page B1-44.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A3-23