ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The System Level Programmers’ Model
CPSR M field and A, I, and F mask bit values on exception entry
On exception entry, the processor mode is set to one of the exception modes and the CPSR[A,I,F] interrupt
disable (mask) bits are set to new values:
the CPSR.I bit is always set to 1, to disable IRQs
the CPSR.M (mode), CPSR.A (asynchronous abort disable), and CPSR.F (FIQ disable) bits are set
to values that depend:
— on the exception type
— if the Security Extensions are implemented, on the security state and some bits of the SCR, see
c1, Secure Configuration Register (SCR) on page B3-106.
The new values are shown in:
Table B1-6, for an implementation that does not include the Security Extensions
Table B1-7 on page B1-37, for an implementation that includes the Security Extensions, when the
security state is Secure (NS == 0).
Table B1-8 on page B1-37, for an implementation that includes the Security Extensions, when the
security state is Non-secure (NS == 1).
In these tables, Unchanged indicates that the bit value is unchanged from its value when the exception was
taken.
Table B1-6 A and F bit values on exception entry, without Security Extensions
Exception Exception mode CPSR.A CPSR.F
Reset Supervisor 1 1
Undefined Instruction Undefined Unchanged Unchanged
Supervisor Call (SVC) Supervisor Unchanged Unchanged
All aborts Abort 1 Unchanged
IRQ IRQ 1 Unchanged
FIQ FIQ 1 1
B1-36 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B