ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Common VFP Subarchitecture Specification
B.3.3 VFP Access Permission faults
When the VFP register bank is disabled by disabling coprocessors 10 and 11 in a coprocessor access control
register, any attempt to use a VFP instruction will bounce. When the VFP register bank is disabled by
clearing the FPEXC.EN bit to 0, any attempt to access a VFP registers, except the FPEXC or FPINST
register, will bounce.
In a system where the VFP can be disabled, handler code must check that the VFP is enabled before
processing a VFP exception.
B.3.4 Unallocated VFP instruction encodings
Unallocated VFP instruction encodings are those coprocessor 10 and 11 instruction encodings that are not
allocated for VFP instructions by ARM.
An unallocated VFP instruction encoding bounces synchronously to the VFP Undefined Instruction handler
code. In this case the VFP state is not modified, the FPEXC.EX bit is set to 0, and the FPEXC.DEX bit is
set to 0. Unallocated instruction exception handling is synchronous.
The VFP exception handler code can check the FPEXC.EX bit, to find out if the VFP is using asynchronous
exception handling to handle a previous exceptional condition.
If FPEXC.EX=1, the support code is called to process a previous exceptional instruction. On return from
the support code the trigger instruction is reissued, and if the trigger instruction is an unallocated instruction
the Undefined Instruction handler is re-entered, with FPEXC.EX=0.
If FPEXC.EN == 1, FPEXC.EX == 0 and FPEXC.DEX == 0, the handler code might have been called as a
result of an unallocated instruction encoding or as a result of an allocated instruction encoding which has
not been implemented:
If the instruction is not a CDP instruction, the instruction is an unallocated instruction encoding and
execution can jump to the unallocated instructions handler provided by the system.
If the instruction is a CDP instruction, the support code must identify whether the instruction is one
that it can handle. If it is not, then execution can jump to the unallocated instructions handler provided
by the system.
B.3.5 Trapped floating-point exception handling
Trapped floating-point exceptions are never handled by hardware. When a trapped exception is detected by
hardware the exception-generating instruction must be re-executed by the support code. The support code
must re-detect and signal the exception.
AppxB-10 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B