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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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The CPUID Identification Scheme<br />

B5.3 Advanced SIMD <strong>and</strong> VFP feature identification registers<br />

When an implementation includes one or both of the optional Advanced SIMD <strong>and</strong> VFP extensions, the<br />

feature identification registers for the extensions are implemented in a common register block. The<br />

extensions reside in the coprocessor space for coprocessors CP10 <strong>and</strong> CP11, <strong>and</strong> the registers are accessed<br />

using the VMRS <strong>and</strong> VMSR instructions. For more information, see Register map of the Advanced SIMD <strong>and</strong><br />

VFP extension system registers on page B1-66.<br />

Table B5-3 lists the feature identification registers for the Advanced SIMD <strong>and</strong> VFP extensions. These are<br />

described in the remainder of this section.<br />

When the Security Extensions are implemented, these registers are Common registers.<br />

B5.3.1 Floating-point System ID Register (FPSID)<br />

In <strong>ARM</strong>v7, the FPSID Register provides top-level information about the floating-point implementation.<br />

Note<br />

In an <strong>ARM</strong>v7 implementation that includes one or both of the Advanced SIMD <strong>and</strong> VFP extensions<br />

the Media <strong>and</strong> VFP Feature registers provide details of the implemented VFP architecture.<br />

The FPSID can be implemented in a system that provides only software emulation of the <strong>ARM</strong><br />

floating-point instructions.<br />

The <strong>ARM</strong>v7 format of the FPSID is:<br />

Implementer, bits [31:24]<br />

Table B5-3 Advanced SIMD <strong>and</strong> VFP feature identification registers<br />

System register Name Description<br />

0b0000 FPSID See Floating-point System ID Register (FPSID)<br />

0b0110 MVFR1 See Media <strong>and</strong> VFP Feature Register 1 (MVFR1) on page B5-38<br />

0b0111 MVFR0 See Media <strong>and</strong> VFP Feature Register 0 (MVFR0) on page B5-36<br />

31 24 23 22 16 15 8 7 4 3 0<br />

Implementer<br />

SW<br />

Subarchitecture Part number Variant Revision<br />

Implementer codes are the same as those used for the Main ID Register, see:<br />

c0, Main ID Register (MIDR) on page B3-81, for a VMSA implementation<br />

c0, Main ID Register (MIDR) on page B4-32, for a PMSA implementation.<br />

For an implementation by <strong>ARM</strong> this field is 0x41, the ASCII code for A.<br />

B5-34 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

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