ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Protected Memory System Architecture (PMSA)
CRn opc1 CRm opc2
c0 0 c0
0
MIDR, Main ID Register
1
CTR, Cache Type Register
2
TCMTR, TCM Type Register, IMPLEMENTATION DEFINED
4
MPUIR, MPU Type Register
5
MPIDR, Multiprocessor Affinity Register
{3,6,7} Aliases of Main ID Register
{c1-c7} {0-7}
CPUID registers
1 c0 0
CCSIDR, Cache Size ID Registers
1
CLIDR, Cache Level ID Register
7
AIDR, Auxiliary ID Register, IMPLEMENTATION DEFINED
2 c0 0
CSSELR, Cache Size Selection Register
c1 0 c0 0
SCTLR, Control Register
1
ACTLR, Auxiliary Control Register, IMPLEMENTATION DEFINED
2 CPACR, Coprocessor Access Control Register
c5 0 c0 {0,1} Fault Status Registers
c1 {0,1}
Auxiliary Fault Status Registers, IMPLEMENTATION DEFINED
c6 0 c0 {0,2}
Fault Address Registers
c1
0
DRBAR, Data Region Base Address Register
1
IRBAR, Instruction Region Base Address Register
2
DRSR, Data Region Size and Enable Register
3
IRSR, Instruction Region Size and Enable Register
4
DRACR, Data Region Access Control Register
5
IRACR, Instruction Region Access Control Register
c2
0
RGNR, MPU Region Number Register
c7 0 c0 4
NOP
c1 {0,6}
Cache maintenance operations, Multiprocessing Extensions
c5 {0,1}
Cache maintenance operations
4
CP15ISB, Instruction barrier operation
{6,7}
Branch predictor maintenance operations
{c6,c10} {1,2} Cache maintenance operations
c10 {4,5}
Data barrier operations
c11
1
DCCMVAU, Cache barrier operation
c13
1
NOP
c14 {1,2}
Cache maintenance operations
c9 {0-7} {c0-c2,c5-c8} {0-7} ‡ Reserved for Branch Predictor, Cache and TCM operations
{c12-c15} {0-7} ‡ Reserved for Performance monitors
c11 {0-7} {c0-c8,c15} {0-7} ‡ Reserved for DMA operations for TCM access
c13 0 c0 1 CONTEXTIDR, Context ID Register
{2-4}
Software Thread Registers
c15 {0-7} {c0-c15} {0-7} ‡ IMPLEMENTATION DEFINED Registers
Read-only Read/Write
Write-only
Bold text = Accessible in User mode
‡ Access depends on the operation
Figure B4-3 CP15 registers in a PMSA implementation
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B4-23