ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

32 encoded as size = 0b10.
The list of registers to store. It must be one of:
{, } encoded as D:Vd = , type = 0b1000
{, } encoded as D:Vd = , type = 0b1001
{, , , }
Contains the base address for the access.
The alignment. It can be one of:
encoded as D:Vd = , type = 0b0011.
64 8-byte alignment, encoded as align = 0b01.
128 16-byte alignment, encoded as align = 0b10.
Instruction Details
256 32-byte alignment, available only if contains four registers, encoded as
align = 0b11
omitted Standard alignment, see Unaligned data access on page A3-5. Encoded as align
= 0b00.
! If present, specifies writeback.
Contains an address offset applied after the access.
For more information about , !, and , see Advanced SIMD addressing mode on page A7-30.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled(); NullCheckIfThumbEE(n);
address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
if wback then R[n] = R[n] + (if register_index then R[m] else 16*regs);
for r = 0 to regs-1
for e = 0 to elements-1
MemU[address,ebytes] = Elem[D[d+r],e,esize];
MemU[address+ebytes,ebytes] = Elem[D[d2+r],e,esize];
address = address + 2*ebytes;
Exceptions
Undefined Instruction, Data Abort.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-773