ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.377 VRSHRN
Vector Rounding Shift Right and Narrow takes each element in a vector, right shifts them by an immediate
value, and places the rounded results in the destination vector. For truncated results, see VSHRN on
page A8-758.
The operand elements can be 16-bit, 32-bit, or 64-bit integers. There is no distinction between signed and
unsigned integers. The destination elements are half the size of the source elements.
Encoding T1 / A1 Advanced SIMD
VRSHRN.I , , #
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 1 1 1 D imm6 Vd 1 0 0 0 0 1 M 1 Vm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 0 1 D imm6 Vd 1 0 0 0 0 1 M 1 Vm
if imm6 == ‘000xxx’ then SEE “Related encodings”;
if Vm == ‘1’ then UNDEFINED;
case imm6 of
when ‘001xxx’ then esize = 8; elements = 8; shift_amount = 16 - UInt(imm6);
when ‘01xxxx’ then esize = 16; elements = 4; shift_amount = 32 - UInt(imm6);
when ‘1xxxxx’ then esize = 32; elements = 2; shift_amount = 64 - UInt(imm6);
d = UInt(D:Vd); m = UInt(M:Vm);
Related encodings See One register and a modified immediate value on page A7-21
A8-740 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B