ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The System Level Programmers’ Model
DSB
ISB
MCR p15, 0, Rx, c1, c0, c0 ; change FI bit in the SCTLR
DSB
ISB
Implementation can define other sequences and circumstances that permit the SCTLR.FI bit to be changed.
When interrupt latency is reduced, this can result in reduced performance overall. Examples of methods that
might be used to reduce interrupt latency are:
disabling Hit-Under-Miss functionality in a processor
the abandoning of restartable external accesses.
These choices permit the processor to react to a pending interrupt faster than would otherwise be the case.
A low interrupt latency configuration permits interrupts and asynchronous aborts to be taken during a
sequence of memory transactions generated by a load/store instruction. For details of what these sequences
are and the consequences of taking interrupts and asynchronous aborts in this way see Single-copy atomicity
on page A3-27.
ARM deprecates any software reliance on the behavior that an interrupt or asynchronous abort cannot occur
in a sequence of memory transactions generated by a single load/store instruction to Normal memory.
Note
A particular case that has shown this reliance is load multiples that load the stack pointer from memory. In
an implementation where an interrupt is taken during the LDM, this can result in corruption of the stack
pointer.
B1.6.8 Wait For Event and Send Event
A multiprocessor operating system requires locking mechanisms to protect data structures from being
accessed simultaneously by multiple processors. These mechanisms prevent the data structures becoming
inconsistent or corrupted if different processors try to make conflicting changes. If a lock is busy, because
a data structure is being used by one processor, it might not be practical for another processor to do anything
except wait for the lock to be released. For example, if a processor is handling an interrupt from a device it
might need to add data received from the device to a queue. If another processor is removing data from the
queue, it will have locked the memory area that holds the queue. The first processor cannot add the new data
until the queue is in a consistent state and the lock has been released. It cannot return from the interrupt
handler until the data has been added to the queue, so it must wait.
Typically, a spin-lock mechanism is provided for these circumstances:
A processor requiring access to the protected data attempts to obtain the lock using single-copy
atomic synchronization primitives such as the ARM Load-Exclusive and Store-Exclusive operations
described in Synchronization and semaphores on page A3-12.
If the processor obtains the lock it performs its memory operation and releases the lock.
B1-44 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B