ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
Cache linefill and eviction bits, bits [1:0]
Either or both of these bits might not be implemented, in which case the bit is RAZ/WI. If
implemented these bits are:
nIL, bit [1] Instruction cache, where separate data and instruction caches are
implemented.
nDL, bit [0] Data or unified cache.
The possible values of an implemented bit are:
0 Request disabling of cache linefills and evictions for memory operations issued
by a debugger when the processor is in Debug state
1 Normal operation of cache linefills and evictions for memory operations issued
by a debugger when the processor is in Debug state.
When cache linefill and eviction is disabled, all memory accesses that would be checked
against a cache are checked against the cache. If a match is found, the cached result is used.
If no match is found the next level of memory is used, but the result is not cached, and no
cache entries are evicted.
The next level of memory can refer to looking in the next level of cache, or to accessing
external memory, depending on the numbers of levels of cache implemented.
When the processor is in Debug state, cache maintenance operations are not affected by the
nDL and nIL control bits, and have their normal architecturally-defined behavior.
The memory hint instructions PLD and PLI have UNPREDICTABLE behavior in Debug state
when the corresponding nDL or nIL control bit is set to 1.
The debug logic reset value of the DBGDSCCR depends on the ARM Debug architecture version:
v7 Debug Debug logic reset values are UNKNOWN. Before issuing operations through the
DBGITR with the processor in Debug state, a debugger must ensure that the
DBGDSCCR has a defined state.
ARMv6 All defined bits reset to 0.
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