ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Register Interfaces
bits [23:16] of DBGDIDR are read into bits [15:8] of the destination register
bits [31:24] of DBGDIDR are read into bits [7:0] of the destination register.
Similarly the bytes of a data value written to a debug register, for example the DBGDSCR,
are reversed in big-endian configuration.
If an ARMv7 processor, with the E bit set for little-endian operation, reads the DBGDIDR of a second
ARMv7 processor with an LDR instruction, then bits [7:0] of the DBGDIDR of the second processor are read
into bits [7:0] of the destination register of the LDR, on the first processor. Similarly, the other bytes of the
DBGDIDR are copied to the corresponding bytes of the destination register. However, if the E bit of the first
processor is set for big-endian operation the bytes are reversed during the LDR operation, with bits [31:24]
of the DBGDIDR of the second processor being read to bits [7:0] of the destination register of the LDR.
Note
The ordering of the bytes in the destination register on the first processor is not affected in any way by the
setting of the CPSR.E bit of the second processor.
These examples assume that no additional manipulation of the data occurs in the interconnect fabric of the
system. For example, an interconnect might perform byte transposition for accesses made across a boundary
between a little-endian subsystem and a big-endian subsystem. Such transformations are beyond the scope
of the architecture.
C6.7.4 Permission summaries for memory-mapped and external debug interfaces
This section gives summaries of the permission controls and their effects for different implementations of
v7 Debug systems. The following subsections describe the access permissions for the two interfaces:
Access permissions for the external debug interface on page C6-47
Access permissions for the memory-mapped interface on page C6-48.
Note
For more information about access permissions in an implementation that includes the OS Save and Restore
mechanism but does not provide access to the DBGOSSRR through the external debug interface, see the
Note in The OS Save and Restore mechanism on page C6-8.
The remaining subsections apply to both interfaces:
Meanings of terms and abbreviations used in this section on page C6-46
Permissions summary for separate debug and core power domains on page C6-48
Permissions summary for SinglePower (debug and core in single power domain) on page C6-50.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C6-45