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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Debug Register Interfaces<br />

Access to all debug registers is not possible if the debug logic is powered down. In this situation:<br />

the system must respond to any access made through the memory-mapped or external debug interface<br />

when the debug power domain is powered down, <strong>and</strong> <strong>ARM</strong> recommends that the system generates<br />

an error response<br />

accesses through the coprocessor interface are UNPREDICTABLE.<br />

The debug logic is powered down:<br />

when the debug power domain is powered down, in an implementation with separate debug <strong>and</strong> core<br />

power domains<br />

when the processor is powered down, in a SinglePower implementation.<br />

C6.5.4 Access to IMPLEMENTATION DEFINED <strong>and</strong> reserved registers<br />

The following subsections describe the responses to accesses to IMPLEMENTATION DEFINED <strong>and</strong> reserved<br />

registers:<br />

Access to implementation defined registers<br />

Access to reserved registers on page C6-30.<br />

Note<br />

There are no IMPLEMENTATION DEFINED or reserved registers in the Baseline CP14 interface <strong>and</strong> therefore<br />

these sections do not say anything about accesses through the Baseline CP14 interface.<br />

Any unused registers in the spaces for IMPLEMENTATION DEFINED registers must behave as reserved<br />

registers. These spaces are register numbers 512-575 <strong>and</strong> 928-959.<br />

Access to IMPLEMENTATION DEFINED registers<br />

When the Debug Software Enable function, described in Permissions in relation to locks on page C6-27, is<br />

disabling software access to the debug registers, Table C6-3 shows how the response to an accesses to an<br />

IMPLEMENTATION DEFINED register depends on the debug interface used for the access.<br />

Table C6-3 Accesses to IMPLEMENTATION DEFINED registers when<br />

Debug Software Enable disables access<br />

Debug interlace used for access a<br />

Response<br />

Memory-mapped interface Error response<br />

Extended CP14 interface Undefined Instruction exception<br />

External debug interface IMPLEMENTATION DEFINED<br />

a. There are no IMPLEMENTATION DEFINED registers in the Baseline CP14<br />

interface.<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. C6-29

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