ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
Register and description
B3.12.2 General behavior of CP15 registers
Table B3-14 Summary of VMSA CP15 register descriptions (continued)
CP15 c12, Security Extensions registers on page B3-148
c12, Vector Base Address Register (VBAR) on page B3-148
c12, Monitor Vector Base Address Register (MVBAR) on page B3-149
c12, Interrupt Status Register (ISR) on page B3-150
CP15 c13, Process, context and thread ID registers on page B3-151
c13, FCSE Process ID Register (FCSEIDR) on page B3-152
c13, Context ID Register (CONTEXTIDR) on page B3-153
CP15 c13 Software Thread ID registers on page B3-154
CP15 c14 is not used, see Unallocated CP15 encodings on page B3-69
CP15 c15, Implementation defined registers on page B3-155
The following sections give information about the general behavior of CP15 registers:
Read-only bits in read/write registers
Unpredictable and undefined behavior for CP15 accesses
Reset behavior of CP15 registers on page B3-70
See also Meaning of fixed bit values in register diagrams on page B3-78.
Read-only bits in read/write registers
Some read/write registers include bits that are read-only. These bits ignore writes.
An example of this is the SCTLR.NMFI bit, bit [27], see c1, System Control Register (SCTLR) on
page B3-96.
UNPREDICTABLE and UNDEFINED behavior for CP15 accesses
In ARMv7 the following operations are UNDEFINED:
all CDP, MCRR, MRRC, LDC and STC operations to CP15
all CDP2, MCR2, MRC2, MCRR2, MRRC2, LDC2 and STC2 operations to CP15.
Unless otherwise indicated in the individual register descriptions:
reserved fields in registers are UNK/SBZP
reserved values of fields can have UNPREDICTABLE effects.
B3-68 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B