ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

E.2 Modified virtual addresses
Fast Context Switch Extension (FCSE)
The 4GB virtual address space is divided into 128 process blocks, each of size 32MB. Each process block
can contain a program that has been compiled to use the address range 0x00000000 to 0x01FFFFFF. For each
of i=0 to 127, process block i runs from address (i × 0x02000000) to address (i × 0x02000000 + 0x01FF FFFF).
The FCSE processes each virtual address for a memory access generated by the ARM processor to produce
a modified virtual address, that is sent to the rest of the memory system to be used in place of the normal
virtual address. For an MMU-based memory system, the process is illustrated in Figure E-1:
Processor
core
Virtual
Address
(VA)
FCSE
Modified
Virtual
Address
(MVA)
MMU
Cache
Physical
Address
(PA)
Figure E-1 Address flow in MMU memory system with FCSE
When the ARM processor generates a memory access, the translation of the Virtual Address (VA) into the
Modified Virtual Address (MVA) is described by the FCSETranslate() function in FCSE translation on
page B3-156.
When the top seven bits of the address are zero, the translation replaces these bits by the value of
FCSEIDR.PID when they are zero, and otherwise the translation leaves the address unchanged. When
FCSEIDR.PID has its reset value of 0b0000000, the translation leaves the address unchanged, meaning that
the FCSE is effectively disabled.
The value of FCSEIDR.PID is also known as the FCSE process ID of the current process. For more
information, see c13, FCSE Process ID Register (FCSEIDR) on page B3-152.
Main
memory
The effect of setting the FCSEIDR to a nonzero value at a time when any translation table entries have
enabled the alternative Context ID, ASID-based support (nG bit == 1) is UNPREDICTABLE. For more
information about ASIDs see About the VMSA on page B3-2.
Note
Virtual addresses are sometimes passed to the memory system as data. For these operations, no address
modification occurs, and MVA = VA.
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