ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

C10.8.4 Claim Tag Clear Register (DBGCLAIMCLR)
Debug Registers Reference
The Claim Tag Clear Register, DBGCLAIMCLR, enables the values of the CLAIM bits, bits [7:0] of the
register, to be:
read
cleared to 0.
For more information about the CLAIM bits and how they might be used, see Claim Tag Set Register
(DBGCLAIMSET) on page C10-92.
The DBGCLAIMCLR Register is:
debug register 1001, at offset 0xFA4
a read/write register, in which:
— writing 0 to a CLAIM bit has no effect
— writing 1 to a CLAIM bit clears that bit to 0
— a read of the register returns the current values of the CLAIM bits
when the Security Extensions are implemented, a Common register.
The format of the DBGCLAIMCLR Register is:
31 8 7 0
Reserved, RAZ/SBZP CLAIM
Bits [31:8] Reserved, RAZ/SBZP.
CLAIM bits, bits [7:0]
Writing a 1 to one of these bits clears the corresponding CLAIM bit to 0. Multiple bits can
be cleared to 0 in a single write operation.
Writing 0 to one of these bits has no effect.
Reading the register returns the current values of these bits.
The debug logic reset value of each of these bits is 0.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-93