ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
The format of the DBGOSLAR is:
31 0
OS Lock Access
OS Lock Access, bits [31:0]
Writing the key value 0xC5ACCE55 to this field locks the debug registers, and resets the
internal counter for the OS Save or Restore operation.
Writing any other value to this register unlocks the debug registers if they are locked.
For details of error responses when accessing the debug registers, see Access permissions on page C6-26.
If bit [0] of the Event Catch Register is set to 1 at the point when the OS Lock is unlocked, an OS Unlock
Catch debug event is generated, see Event Catch Register (DBGECR) on page C10-78.
C10.6.2 OS Lock Status Register (DBGOSLSR)
The OS Lock Status Register, DBGOSLSR, provides status information for the OS Lock.
The DBGOSLSR is:
debug register 193, at offset 0x304
a read-only register
only defined in v7 Debug
when the Security Extensions are implemented, a Common register.
Note
In any v7 Debug implementation you can read the DBGOSLSR to detect whether the OS Save and Restore
mechanism is implemented. If it is not implemented the read of the DBGOSLSR returns zero.
In v6 Debug and v6.1 Debug, register 193 is not defined.
The format of the DBGOSLSR is:
31 3
2 1
Reserved, UNK
Bits [31:3] Reserved, UNK.
32-bit access, bit [2]
32-bit access
Locked
Lock implemented
This bit is always RAZ. It indicates that a 32-bit access is needed to write the key to the OS
Lock Access Register.
C10-76 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B
0