ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
VCVT..F64 , ,# op =1, sf =1
VCVT..F32 , , # op =1, sf =0
VCVT.F64. , , # op =0, sf =1
VCVT.F32. , , # op =0, sf =0
where:
See Standard assembler syntax fields on page A8-7.
The data type for the fixed-point number. It must be one of:
S16 encoded as U = 0, sx = 0
U16 encoded as U = 1, sx = 0
S32 encoded as U = 0, sx = 1
U32 encoded as U = 1, sx = 1.
The destination and operand register, for a double-precision operand.
The destination and operand register, for a single-precision operand.
The number of fraction bits in the fixed-point number:
Operation
Instruction Details
If is S16 or U16, must be in the range 0-16. (16 - ) is encoded in
[imm4,i]
I f is S32 or U32, must be in the range 1-32. (32 - ) is encoded in
[imm4,i].
if ConditionPassed() then
EncodingSpecificOperations(); CheckVFPEnabled(TRUE);
if to_fixed then
if dp_operation then
result = FPToFixed(D[d], size, frac_bits, unsigned, round_zero, TRUE);
D[d] = if unsigned then ZeroExtend(result, 64) else SignExtend(result, 64);
else
result = FPToFixed(S[m], size, frac_bits, unsigned, round_zero, TRUE);
S[d] = if unsigned then ZeroExtend(result, 32) else SignExtend(result, 32);
else
if dp_operation then
D[d] = FixedToFP(D[d], 64, frac_bits, unsigned, round_nearest, TRUE);
else
S[d] = FixedToFP(S[d], 32, frac_bits, unsigned, round_nearest, TRUE);
Exceptions
Undefined Instruction.
Floating-point exceptions: Input Denormal, Invalid Operation, and Inexact.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-583