ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
ExT, bit [12] External abort type. This bit can be used to provide an IMPLEMENTATION DEFINED
classification of external aborts.
FS, bits [10,3:0]
For aborts other than external aborts this bit always returns 0.
Fault status bits. For the valid encodings of these bits in an ARMv7-A implementation with
a VMSA, see Table B3-11 on page B3-50.
All encodings not shown in the table are reserved.
For information about using the IFSR see Fault Status and Fault Address registers in a VMSA
implementation on page B3-48.
Accessing the IFSR
To access the IFSR you read or write the CP15 registers with set to 0, set to c5, set to c0,
and set to 1. For example:
MRC p15,0,,c5,c0,1 ; Read CP15 Instruction Fault Status Register
MCR p15,0,,c5,c0,1 ; Write CP15 Instruction Fault Status Register
c5, Auxiliary Data and Instruction Fault Status Registers (ADFSR and AIFSR)
The Auxiliary Data Fault Status Register (ADFSR) and the Auxiliary Instruction Fault Status Register
(AIFSR) enable the system to return additional IMPLEMENTATION DEFINED fault status information, see
Auxiliary Fault Status Registers on page B3-53.
The ADFSR and AIFSR are:
32-bit read/write registers
accessible only in privileged modes
when the Security Extensions are implemented, Banked registers
introduced in ARMv7.
The formats of the ADFSR and AIFSR are IMPLEMENTATION DEFINED.
Accessing the ADFSR and AIFSR
To access the ADFSR or AIFSR you read or write the CP15 registers with set to 0, set to c5,
set to c1, and set to:
0 for the ADFSR
1 for the AIFSR.
For example:
MRC p15,0,,c5,c1,0 ; Read CP15 Auxiliary Data Fault Status Register
MCR p15,0,,c5,c1,0 ; Write CP15 Auxiliary Data Fault Status Register
MRC p15,0,,c5,c1,1 ; Read CP15 Auxiliary Instruction Fault Status Register
MCR p15,0,,c5,c1,1 ; Write CP15 Auxiliary Instruction Fault Status Register
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