ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

NS_DL, bit [0]
ARMv6 Differences
Non-secure data cache linefill. Can be used to disable data cache linefill for Non-secure
regions. The possible values of this bit are:
0 Data cache linefill enabled. This corresponds to normal cache operation.
1 Data cache linefill disabled for regions marked as Non-secure.
It might be necessary to ensure that cache contents are not changed, for example when debugging or when
processing an interruptible cache operation. The CBOR provides this option.
For example, Clean All, and Clean and Invalidate All operations in Non-secure state might not prevent fast
interrupts to the Secure side if the FW bit in the SCR is set to 0. In this case, operations in the Secure state
can read or write Non-secure locations in the cache. Such operations might cause the cache to contain valid
or dirty Non-secure entries after the Non-secure Clean All and Clean and Invalidate All operation has
completed. To prevent this problem, the Secure state must be:
prevented from allocating Non-secure entries into the cache by disabling Non-secure linefill
made to treat all writes to Non-secure regions that hit in the cache as being write-though by forcing
Non-secure Write-Through.
The CBOR provides separate controls for Secure and Non-secure memory regions, and can be used to
prevent cache linefill, or to force Write-Through operation, while leaving the caches enabled. The controls
for Secure memory regions can be accessed only when the processor is in the Secure state.
Accessing the CBOR
To access the CBOR you read or write the CP15 registers with set to 0, set to c9, set to
c8, and set to 0. For example:
MRC p15, 0, , c9, c8, 0 ; Read CP15 Cache Behavior Override Register
MCR p15, 0, , c9, c8, 0 ; Write CP15 Cache Behavior Override Register
c9, TCM Non-Secure Access Control Registers, DTCM-NSACR and ITCM-NSACR
The Data TCM Non-Secure Access Control Register (DTCM-NSACR) defines the accessibility of the Data
TCM Region Register when the processor is in Non-secure state.
The Instruction TCM Non-Secure Access Control Register (ITCM-NSACR) defines the accessibility of the
current Instruction or Unified TCM Region Register when the processor is in Non-secure state.
For information on TCM support, see Tightly Coupled Memory (TCM) support on page AppxG-23.
The TCM-NSACR registers are:
32-bit read/write registers
accessible only in privileged modes
implemented only in a VMSAv6 implementation that includes the Security Extensions
Secure registers, see Restricted access CP15 registers on page B3-73.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxG-51