ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.273 VADDHN
Vector Add and Narrow, returning High Half adds corresponding elements in two quadword vectors, and
places the most significant half of each result in a doubleword vector. The results are truncated. (For rounded
results, see VRADDHN on page A8-726).
The operand elements can be 16-bit, 32-bit, or 64-bit integers. There is no distinction between signed and
unsigned integers.
Encoding T1 / A1 Advanced SIMD
VADDHN. , ,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 1 1 1 D size Vn Vd 0 1 0 0 N 0 M 0 Vm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 0 1 D size Vn Vd 0 1 0 0 N 0 M 0 Vm
if size == ‘11’ then SEE “Related encodings”;
if Vn == ‘1’ || Vm == ‘1’ then UNDEFINED;
esize = 8