ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Protected Memory System Architecture (PMSA)
C, bit [2] Cache enable bit: This is a global enable bit for data and unified caches:
0 Data and unified caches disabled
1 Data and unified caches enabled.
If the system does not implement any data or unified caches that can be accessed by the
processor, at any level of the memory hierarchy, this bit is RAZ/WI.
If the system implements any data or unified caches that can be accessed by the processor
then it must be possible to disable them by setting this bit to 0.
Cache enabling and disabling on page B2-8 describes the effect of enabling the caches.
A, bit [1] Alignment bit. This is the enable bit for Alignment fault checking:
0 Alignment fault checking disabled
1 Alignment fault checking enabled.
For more information, see Alignment fault on page B4-14.
M, bit [0] MPU enable bit. This is a global enable bit for the MPU:
0 MPU disabled
1 MPU enabled.
For more information, see Enabling and disabling the MPU on page B4-5.
Reset value of the SCTLR
The SCTLR has a defined reset value that is IMPLEMENTATION DEFINED. There are different types of bit in
the SCTLR:
Some bits are defined as RAZ or RAO, and have the same value in all PMSAv7 implementations.
Figure B4-6 on page B4-50 shows the values of these bits.
Some bits are read-only and either:
— have an IMPLEMENTATION DEFINED value
— have a value that is determined by a configuration input signal.
Some bits are read/write and either:
— reset to zero
— reset to an IMPLEMENTATION DEFINED value
— reset to a value that is determined by a configuration input signal.
Figure B4-6 on page B4-50 shows the reset value, or how the reset value is defined, for each bit of the
SCTLR. It also shows the possible values of each half byte of the register.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B4-49