05.02.2013 Views

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

SHOW MORE
SHOW LESS

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

Application Level Memory Model<br />

A3.6 Access rights<br />

<strong>ARM</strong>v7 includes additional attributes for memory regions, that enable:<br />

Data accesses to be restricted, based on the privilege of the access. See Privilege level access controls<br />

for data accesses.<br />

Instruction fetches to be restricted, based on the privilege of the process or thread making the fetch.<br />

See Privilege level access controls for instruction accesses.<br />

On a system that implements the Security Extensions, accesses to be restricted to memory accesses<br />

with the Secure memory attribute. See Memory region security status on page A3-39.<br />

A3.6.1 Privilege level access controls for data accesses<br />

The memory attributes can define that a memory region is:<br />

not accessible to any accesses<br />

accessible only to Privileged accesses<br />

accessible to Privileged <strong>and</strong> Unprivileged accesses.<br />

The access privilege level is defined separately for explicit read <strong>and</strong> explicit write accesses. However, a<br />

system that defines the memory attributes is not required to support all combinations of memory attributes<br />

for read <strong>and</strong> write accesses.<br />

A Privileged access is an access made during privileged execution, as a result of a load or store operation<br />

other than LDRT, STRT, LDRBT, STRBT, LDRHT, STRHT, LDRSHT, or LDRSBT.<br />

An Unprivileged access is an access made as a result of load or store operation performed in one of these<br />

cases:<br />

when the processor is in an unprivileged mode<br />

when the processor is in any mode <strong>and</strong> the access is made as a result of a LDRT, STRT, LDRBT, STRBT,<br />

LDRHT, STRHT, LDRSHT, or LDRSBT instruction.<br />

A Data Abort exception is generated if the processor attempts a data access that the access rights do not<br />

permit. For example, a Data Abort exception is generated if the processor is in unprivileged mode <strong>and</strong><br />

attempts to access a memory region that is marked as only accessible to Privileged accesses.<br />

A3.6.2 Privilege level access controls for instruction accesses<br />

Memory attributes can define that a memory region is:<br />

Not accessible for execution<br />

Accessible for execution by Privileged processes only<br />

Accessible for execution by Privileged <strong>and</strong> Unprivileged processes.<br />

To define the instruction access rights to a memory region, the memory attributes describe, separately, for<br />

the region:<br />

its read access rights, see Privilege level access controls for data accesses<br />

A3-38 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!