ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Non-invasive Debug Authentication
C7.3 Effects of non-invasive debug authentication
The following sections describe the effects of the non-invasive debug authentication on the non-invasive
debug components:
Performance monitors
Trace on page C7-7
Reads of the Program Counter sampling registers on page C8-3.
C7.3.1 Performance monitors
Performance monitors provide a non-invasive debug feature, and are controlled by the non-invasive debug
authentication signals. For more information, see Chapter C9 Performance Monitors.
The cycle counter, PMCCNTR, is not controlled by the non-invasive debug authentication signals. However,
setting the PMCR.DP flag to 1 disables PMCCNTR counting in regions of code where the event counters
are disabled. For details see c9, Performance Monitor Control Register (PMCR) on page C10-105.
Table C7-3 describes the behavior of the performance monitors when non-invasive debug is disabled or not
permitted, and in Debug state.
Table C7-3 Behavior of performance monitors when non-invasive debug not permitted
Debug
state
Non-invasive debug
permitted and enabled
PMCR.DP a
Event counters enabled
and events exported a, b
Yes x x No No
No Yes x Yes Yes
No No 0 No Yes
No No 1 No No
a. See c9, Performance Monitor Control Register (PMCR) on page C10-105.
b. The events are exported only if the PMCR.X bit is set to 1.
PMCCNTR
enabled
The performance monitors are not intended to be completely accurate, see Accuracy of the performance
monitors on page C9-5. In particular, some inaccuracy is permitted at the point of changing security state.
However, to avoid the leaking of information from the Secure state, the permitted inaccuracy is that
non-prohibited transactions can be uncounted. Prohibited transactions must not be counted.
Entry to and exit from Debug state can also disturb the normal running of the processor, causing additional
inaccuracy in the performance monitors. Disabling the counters while in Debug state limits the extent of this
inaccuracy. Implementations can limit this inaccuracy to a greater extent, for example by disabling the
counters as soon as possible during the Debug state entry sequence.
C7-6 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B