ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
The format of the FCSEIDR is:
31 25 24 0
PID UNK/SBZP
PID, bits [31:25]
The current Process ID, for the FCSE. If the FCSE is not implemented this field is RAZ/WI.
Bits [24:0] Reserved. If the FCSE is not implemented this field is RAZ/WI.
If the FCSE is implemented, the value of this field is UNKNOWN on reads and
Should-Be-Zero-or-Preserved on writes.
Note
When the PID is written, the overall virtual-to-physical address mapping changes. Because of this,
you must ensure that instructions that might have been prefetched already are not affected by the
address mapping change.
From ARMv6, use of the FCSE is deprecated, and in ARMv7 the FCSE is optional.
Accessing the FCSEIDR
To access the FCSEIDR you read or write the CP15 registers with set to 0, set to c13, set
to c0, and set to 0. For example:
MRC p15,0,,c13,c0,0 ; Read CP15 FCSE PID Register
MCR p15,0,,c13,c0,0 ; Write CP15 FCSE PID Register
B3.12.45 c13, Context ID Register (CONTEXTIDR)
The Context ID Register, CONTEXTIDR, identifies the current:
Process Identifier (PROCID)
Address Space Identifier (ASID).
The value of the whole of this register is called the Context ID and is used by:
the debug logic, for Linked and Unlinked Context ID matching, see Breakpoint debug events on
page C3-5 and Watchpoint debug events on page C3-15.
the trace logic, to identify the current process.
The ASID field value is used by many memory management functions.
The CONTEXTIDR is:
a 32-bit read/write register
accessible only in privileged modes
when the Security Extensions are implemented, a Banked register.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B3-153