ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Table C10-28 shows the behavior of this bit on reads and writes.
Debug Registers Reference
The contents of the PMINTENSET Register are UNKNOWN on a core logic reset. To avoid spurious
interrupts being generated, software must set the interrupt enable values before enabling any of the counters.
Interrupts are not signaled if the PMCR.E Enable bit is set to 0.
When an interrupt is signaled, it can be removed by clearing the overflow flag for the counter in the
PMOVSR Register, see c9, Overflow Flag Status Register (PMOVSR) on page C10-110.
Note
Table C10-28 Read and write bit values for the PMINTENSET Register
ARM expects that the interrupt request that can be generated on a counter overflow is also exported from
the processor, meaning it can be factored into a system interrupt controller if applicable. This means that
normally the system will have more levels of control of the interrupt generated.
C10.9.12 c9, Interrupt Enable Clear Register (PMINTENCLR)
Value Meaning on read Action on write
0 Interrupt disabled No action, write is ignored
1 Interrupt enabled Enable interrupt
The Interrupt Enable Clear Register, PMINTENCLR, disables the generation of interrupt requests on
overflows from:
the Cycle Count Register, PMCCNTR
each implemented event counter, PMNx.
Reading the PMINTENCLR Register shows which overflow interrupts are enabled. Counter overflow
interrupts must be enabled using the PMINTENSET Register, see c9, Interrupt Enable Set Register
(PMINTENSET) on page C10-118.
The PMINTENCLR Register is:
A 32-bit read/write CP15 register:
— reading the register shows which overflow interrupts are enabled
— writing a 1 to a bit of the register disables the corresponding overflow interrupt
— writing a 0 to a bit of the register has no effect.
Accessible only in privileged modes.
The instructions that access the PMINTENCLR Register are always UNDEFINED in User mode, even
if the PMUSERENR.EN flag is set to 1, see c9, User Enable Register (PMUSERENR) on
page C10-117.
When the Security Extensions are implemented, a Common register.
Accessed using an MRC or MCR command with set to c9, set to 0, set to c14, and
set to 2.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-119