ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Note
Debug Registers Reference
ARMv7 only defines Debug Peripheral ID Registers 0 to 4, and reserves space for Debug Peripheral
ID Registers 5 to 7.
The register number order of the Debug Peripheral ID Registers does not match the numerical order
ID0 to ID7, see Table C10-22.
Table C10-22 lists the Debug Peripheral Identification Registers in register number order.
Register:
Number Offset
Table C10-22 Debug Peripheral Identification Registers
Description Reference
1012 0xFD0 Debug Peripheral ID4 DBGPID4 on page C10-102
1013 0xFD4 Reserved for Debug Peripheral ID5, DBGPID5 -
1014 0xFD8 Reserved for Debug Peripheral ID6, DBGPID6 -
1015 0xFDC Reserved for Debug Peripheral ID7, DBGPID7 -
1016 0xFE0 Debug Peripheral ID0 DBGPID0 on page C10-101
1017 0xFE4 Debug Peripheral ID1 DBGPID1 on page C10-101
1018 0xFE8 Debug Peripheral ID2 DBGPID2 on page C10-101
1019 0xFEC Debug Peripheral ID3 DBGPID0 on page C10-101
Only bits [7:0] of each Debug Peripheral ID Register are used. This means that the format of each register is:
31 8 7 0
Reserved, RAZ Peripheral ID data
The eight Debug Peripheral ID Registers can be considered as defining a single 64-bit Peripheral ID, as
shown in Figure C10-1.
DBGPID7
Actual Peripheral ID Register fields
DBGPID6 DBGPID5 DBGPID4 DBGPID3 DBGPID2 DBGPID1 DBGPID0
7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0
63 56 55 48 47 40 39 32 31 24 23 16 15
8 7
0
Conceptual 64-bit Peripheral ID
Figure C10-1 Mapping between Debug Peripheral ID Registers and a 64-bit Peripheral ID value
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-99