ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Register Interfaces
When the processor is in Non-debug state, all User mode accesses to the Extended CP14 interface registers
are UNDEFINED.
For example, in privileged modes the following instruction reads the value of DBGWVR7, register 103, if
at least 8 watchpoints are implemented, and is UNPREDICTABLE otherwise:
MRC p14,0,,c0,c7,6
Note
The access permissions in Table C6-11 on page C6-39 and Table C6-12 on page C6-40 have precedence
over the behavior in Table C6-13 on page C6-40. For example, even if at least 8 watchpoints are
implemented, the following instruction is UNDEFINED in all processor modes when the Debug Software
Enable function is disabled:
MRC p14,0,,c0,c7,6
v6 Debug and v6.1 Debug CP14 debug registers access permissions
In v6 Debug and v6.1 Debug, access to registers other than the DBGDIDR, DBGDSCR, DBGDTRRX, and
DBGDTRTX is not permitted if Halting debug-mode is selected. The Debug Software Enable function, the
Sticky Power-down status bit and the OS Lock are not implemented, and there are fewer CP14 debug
registers than in the v7 Debug Extended CP14 interface.
For v6 Debug and v6.1 Debug:
Table C6-8 on page C6-36 shows the access permissions for the Baseline CP14 debug registers
Table C6-14 shows the access permissions for the other CP14 debug registers.
Table C6-14 Access to CP14 debug registers, v6 Debug and v6.1 Debug
Conditions a
Debug state Processor mode DBGDSCR[15:14] c
Yes X XX Proceed
Other CP14 debug
instructions b
No User XX UNDEFINED
No Privileged 00 (None) UNDEFINED
No Privileged X1 (Halting) UNDEFINED
No Privileged 10 (Monitor) Proceed
a. The accesses in this table are not affected by the value of the DBGDSCR.UDCCdis bit.
b. All instructions with == 0b000 and == 0b0000, except for read accesses to DBGDIDR,
DBGDSAR, DBGDRAR, DBGDSCRint, and DBGDTRRXint, and write accesses to DBGDSCRint
and DBGDTRTXint. See also Table C6-15 on page C6-42.
c. MDBGen and HDBGen bits, debug-mode enable and select bits.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C6-41