ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
B3.10 Translation Lookaside Buffers (TLBs)
Translation Lookaside Buffers (TLBs) are an implementation technique that caches translations or
translation table entries. TLBs avoid the requirement for every memory access to perform a translation table
lookup. The ARM architecture does not specify the exact form of the TLB structures for any design. In a
similar way to the requirements for caches, the architecture only defines certain principles for TLBs:
The architecture has a concept of an entry locked down in the TLB. The method by which lockdown
is achieved is IMPLEMENTATION DEFINED, and an implementation might not support lockdown.
An unlocked entry in the TLB is not guaranteed to remain in the TLB.
A locked entry in the TLB is guaranteed to remain in the TLB. However, a locked entry in a TLB
might be updated by subsequent updates to the translation tables. Therefore it is not guaranteed to
remain incoherent with an entry in the translation table if a change is made to the translation tables.
A translation table entry that returns a Translation fault or an Access fault is guaranteed not to be held
in the TLB. However a translation table entry that returns a Domain fault or a Permission fault might
be held in the TLB.
Any translation table entry that does not return a Translation or Access fault might be allocated to an
enabled TLB at any time. The only translation table entries guaranteed not to be held in the TLB are
those that return a Translation or Access fault.
Software can rely on the fact that between disabling and re-enabling the MMU, entries in the TLB
have not have been corrupted to give incorrect translations.
B3.10.1 Global and non-global regions in the virtual memory map
The VMSA permits the virtual memory map to be divided into global and non-global regions, distinguished
by the nG bit in the translation table descriptors:
nG == 0 The translation is global.
nG == 1 The translation is process specific, meaning it relates to the current ASID, as defined by the
CONTEXTIDR.
Each non-global region has an associated Address Space Identifier (ASID). These identifiers enable
different translation table mappings to co-exist in a caching structure such as a TLB. This means that a new
mapping of a non-global memory region can be created without removing previous mappings.
For a symmetric multiprocessor cluster where a single operating system is running on the set of processing
elements, ARMv7 requires all ASID values to be assigned uniquely. In other words, each ASID value must
have the same meaning to all processing elements in the system.
The use of non-global pages when FCSEIDR[31:25] is not 0b0000000 is UNPREDICTABLE.
B3-54 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B