ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The CPUID Identification Scheme
Single-precision, bits [7:4]
A value of 0b0001 or 0b0010 indicates support for all VFP double-precision instructions in
the supported version of VFP, except that, in addition to this field being nonzero:
FSQRTD is only available if the Square root field is 0b0001
FDIVD is only available if the Divide field is 0b0001
conversion between double-precision and single-precision is only available if the
single-precision field is nonzero.
Indicates the hardware support for VFP single-precision operations. Permitted values are:
0b0000 Not supported in hardware.
0b0001 Supported, VFPv2.
0b0010 Supported, VFPv3.
VFPv3 adds an instruction to load a single-precision floating-point constant,
and conversions between single-precision and fixed-point values.
A value of 0b0001 or 0b0010 indicates support for all VFP single-precision instructions in
the supported version of VFP, except that, in addition to this field being nonzero:
FSQRTS is only available if the Square root field is 0b0001
FDIVS is only available if the Divide field is 0b0001
conversion between double-precision and single-precision is only available if the
double-precision field is nonzero.
A_SIMD registers, bits [3:0]
Indicates support for the Advanced SIMD register bank. Permitted values are:
0b0000 Not supported.
0b0001 Supported, 16 x 64-bit registers.
0b0010 Supported, 32 x 64-bit registers.
If this field is nonzero:
all VFP LDC, STC, MCR, and MRC instructions are supported
if the CPUID register shows that the MCRR and MRRC instructions are supported then the
corresponding VFP instructions are supported.
Media and VFP Feature Register 1 (MVFR1)
The format of the MVFR1 register is:
31 28 27 24 23 20 19
16 15 12 11 8 7 4 3 0
Reserved,
RAZ
VFP
HPFP
Bits [31:28] Reserved, RAZ.
A_SIMD
HPFP
A_SIMD
SPFP
A_SIMD
integer
A_SIMD
load/store
D_NaN
mode
FtZ
mode
B5-38 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B