ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Advanced SIMD and VFP Instruction Encoding
A7.7.1 Advanced SIMD addressing mode
All the element and structure load/store instructions use this addressing mode. There is a choice of three
formats:
[{@}] The address is contained in ARM core register Rn.
Rn is not updated by this instruction.
Encoded as Rm = 0b1111.
If Rn is encoded as 0b1111, the instruction is UNPREDICTABLE.
[{@}]! The address is contained in ARM core register Rn.
Rn is updated by this instruction: Rn = Rn + transfer_size
Encoded as Rm = 0b1101.
transfer_size is the number of bytes transferred by the instruction. This means that,
after the instruction is executed, Rn points to the address in memory immediately
following the last address loaded from or stored to.
If Rn is encoded as 0b1111, the instruction is UNPREDICTABLE.
This addressing mode can also be written as:
[{@align}], #
However, disassembly produces the [{@align}]! form.
[{@}],
The address is contained in ARM core register .
Rn is updated by this instruction: Rn = Rn + Rm
Encoded as Rm = Rm. Rm must not be encoded as 0b1111 or 0b1101 (the PC or
the SP).
If Rn is encoded as 0b1111, the instruction is UNPREDICTABLE.
In all cases, specifies an optional alignment. Details are given in the individual instruction
descriptions.
A7-30 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B