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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Debug Registers <strong>Reference</strong><br />

C10.5 Software debug event registers<br />

This section contains the following subsections:<br />

Breakpoint Value Registers (DBGBVR)<br />

Breakpoint Control Registers (DBGBCR) on page C10-49<br />

Watchpoint Value Registers (DBGWVR) on page C10-60<br />

Watchpoint Control Registers (DBGWCR) on page C10-61<br />

Vector Catch Register (DBGVCR) on page C10-67.<br />

In addition, when the OS Save <strong>and</strong> Restore mechanism is implemented, the Event Catch Register can be<br />

used to enable generation of a debug event when the OS Lock is unlocked, see Event Catch Register<br />

(DBGECR) on page C10-78.<br />

C10.5.1 Breakpoint Value Registers (DBGBVR)<br />

A Breakpoint Value Register, DBGBVR, holds a value for use in breakpoint matching. The value is either<br />

an Instruction Virtual Address (IVA) or a Context ID. Each DBGBVR is associated with a DBGBCR to form<br />

a Breakpoint Register Pair (BRP). DBGBVRn is associated with DBGBCRn to form BRPn, where n takes<br />

the values from 0 to 15. A debug event is generated when an instruction that matches the BRP is committed<br />

for execution. For more information, see Breakpoint debug events on page C3-5.<br />

A breakpoint can be set on any one of:<br />

an IVA match or mismatch<br />

a Context ID match<br />

an IVA match or mismatch occurring with a Context ID match.<br />

For the third case:<br />

two BRPs must be linked, see Breakpoint Control Registers (DBGBCR) on page C10-49.<br />

a debug event is generated when, on the same instruction, both:<br />

— the IVA matches or mismatches, as required<br />

— the Context ID matches.<br />

See Memory addresses on page C3-23 for a definition of the IVA used to program a DBGBVR.<br />

Note<br />

Some BRPs might not support Context ID comparison. For more information, see the description of the<br />

DBGDIDR.CTX_CMPs field in Debug ID Register (DBGDIDR) on page C10-3.<br />

The DBGBVRs are:<br />

debug registers 64-79, at offsets 0x100-0x13C<br />

read/write registers<br />

when the Security Extensions are implemented, Common registers.<br />

C10-48 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

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