ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
The format of the VBAR is:
31 5 4 0
Vector_Base_Address (0) (0) (0) (0) (0)
The Secure copy of the VBAR holds the vector base address for the Secure state, described as the Secure
exception base address
The Non-secure copy of the VBAR holds the vector base address for the Non-secure state, described as the
Non-secure exception base address.
Vector_Base_Address, bits [31:5]
Bits [31:5] of the base address of the normal exception vectors. Bits [4:0] of an exception
vector is the exception offset, see Table B1-3 on page B1-31.
Bits [4:0] Reserved, UNK/SBZP.
For details of how the VBAR registers are used to determine the exception addresses see Exception vectors
and the exception base address on page B1-30.
Accessing the VBAR
To access the VBAR you read or write the CP15 registers with set to 0, set to c12, set to
c0, and set to 0. For example:
MRC p15,0,,c12,c0,0 ; Read CP15 Vector Base Address Register
MCR p15,0,,c12,c0,0 ; Write CP15 Vector Base Address Register
B3.12.41 c12, Monitor Vector Base Address Register (MVBAR)
The Monitor Vector Base Address Register, MVBAR, provides the exception base address for all exceptions
that are handled in Monitor mode, see Exception vectors and the exception base address on page B1-30.
The MVBAR is:
present only when the Security Extensions are implemented
a 32-bit read/write register
accessible in Secure privileged modes only
a Restricted access register, meaning it exists only in the Secure state.
The format of the MVBAR is:
31 5 4 0
Monitor_Vector_Base_Address (0) (0) (0) (0) (0)
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B3-149