ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Protected Memory System Architecture (PMSA)
Address
range
0xFFFFFFFF
-0xF0000000
0xFFFFFFFF -
0xF0000000
0xEFFFFFFF -
0xC0000000
0xBFFFFFFF -
0xA0000000
0x9FFFFFFF -
0x80000000
0x7FFFFFFF -
0x60000000
0x5FFFFFFF -
0x40000000
0x3FFFFFFF -
0x00000000
Instruction and data prefetch operations work as normal, based on the default memory map:
— Data prefetch operations have no effect if the data cache is disabled
— Instruction prefetch operations have no effect if the instruction cache is disabled.
The Outer memory attributes are the same as those for the Inner memory system.
The default memory map
The PMSAv7 default memory map is fixed and not configurable, and is shown in:
Table B4-1 for the instruction access attributes
Table B4-2 on page B4-7 for the data access attributes.
The regions of the default memory map are identical in both tables. The information about the memory map
is split into two tables only to improve the presentation of the information.
HIVECS
Table B4-1 Default memory map, showing instruction access attributes
Instruction memory type
Caching enabled a Caching disabled a
Execute Never, XN
0 Not applicable Not applicable Execute Never
1 b Normal, Non-cacheable Normal, Non-cacheable Execution permitted
X Not applicable Not applicable Execute Never
X Not applicable Not applicable Execute Never
X Not applicable Not applicable Execute Never
X
X
X
Normal, Non-shareable,
Write-Through Cacheable
Normal, Non-shareable,
Write-Through Cacheable
Normal, Non-shareable,
Write-Through Cacheable
Normal, Non-shareable,
Non-cacheable
Normal, Non-shareable,
Non-cacheable
Normal, Non-shareable,
Non-cacheable
Execution permitted
Execution permitted
Execution permitted
a. When separate instruction and data caches are implemented, caching is enabled for instruction accesses if the
instruction caches are enabled. When unified caches are implemented caching is enabled if the data or unified caches
are enabled. See the descriptions of the C and I bits in c1, System Control Register (SCTLR) on page B4-45.
b. Use of HIVECS == 1 is deprecated in PMSAv7, see Exception vectors and the exception base address on page B1-30.
B4-6 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B