ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Register or operation
General conditions applying to Format A, B, and C lockdown
The instructions used to access the CP15 c9 lockdown registers are as follows:
MCR p15, 0, , c9, c0, 0 ; write Data or unified Cache Lockdown Register
MRC p15, 0, , c9, c0, 0 ; read Data or unified Cache Lockdown Register
MCR p15, 0, , c9, c0, 1 ; write Instruction Cache Lockdown Register
MRC p15, 0, , c9, c0, 1 ; read Instruction Cache Lockdown Register
ARMv4 and ARMv5 Differences
Unlock instruction cache D c9 0 c5 1
Format D Data or unified Cache Lockdown Register, DCLR2 D c9 0 c6 0
Unlock data cache D c9 0 c6 1
Formats A, B, and C all use cache ways for lockdown granularity. Granularity is defined by the lockdown
block, and a cache locking scheme can use any number of lockdown blocks from 1 to (ASSOCIATIVITY-1).
If N lockdown blocks are locked down, they have indices 0 to N-1, and lockdown blocks N to
(ASSOCIATIVITY-1) are available for normal cache operation.
A cache way based lockdown implementation must not lock down the entire cache. At least one cache way
must be left for normal cache operation, otherwise behavior is UNPREDICTABLE.
The lockdown blocks are indexed from 0 to (ASSOCIATIVITY-1). The cache lines in a lockdown block are
chosen to have the same WAY number as the lockdown block index value. So lockdown block n consists of
the cache line with index n from each cache set, and n takes the values from n == 0 to
n == (ASSOCIATIVITY-1).
Where NSETS is the number of sets, and LINELEN is the cache line length, each lockdown block can hold
NSETS memory cache lines, provided each of the memory cache lines is associated with a different cache
set. ARM recommends that systems are designed so that each lockdown block contains a set of NSETS
consecutive memory cache lines. This is NSETS × LINELEN consecutive memory locations, starting at a
cache line boundary. Such sets are easily identified and are guaranteed to consist of one cache line associated
with each cache set.
Formats A and B lockdown
Formats A and B use a WAY field that is chosen to be wide enough to hold the way number of any lockdown
block. Its width, W, is given by W = log2(ASSOCIATIVITY), rounded up to the nearest integer if necessary.
The format of a Format A lockdown register is:
Table H-24 cache lockdown register support (continued)
Lockdown
formats
CRn opc1 CRm opc2
31 32–W 31–W 0
WAY UNK/SBZ
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxH-53