ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
C10.7 Memory system control registers
Support for the Memory system control registers can depend on the Debug architecture version:
v6 Debug and v6.1 Debug
In some v6 Debug and v6.1 Debug implementations a Cache Behavior Override Register
(CBOR) is provided in an IMPLEMENTATION DEFINED region of the CP15 register space. In
addition, particularly in v6.1 Debug implementations, the Debug State MMU Control
Register (DBGDSMCR) and Debug State Cache Control Register (DBGDSCCR) might be
implemented as IMPLEMENTATION DEFINED extensions to CP14, as described below.
v6 Debug and v6.1 Debug do not require these registers. However, ARM recommends these
features to assist debuggers to maintaining memory coherency, avoiding costly explicit
coherency operations.
v7 Debug In v7 Debug, the DBGDSMCR and DBGDSCCR are required, but there can be
IMPLEMENTATION DEFINED limits on their behavior. The CP15 register CBOR remains
IMPLEMENTATION DEFINED.
The Memory system control registers are described in the subsections:
Debug State Cache Control Register (DBGDSCCR) on page C10-81
Debug State MMU Control Register (DBGDSMCR) on page C10-84.
The Debug State Cache Control Register (DBGDSCCR) and Debug State MMU Control Register
(DBGDSMCR) control cache and TLB behavior for memory operations issued by a debugger when the
processor is in Debug state. They enable a debugger to request the minimum amount of intrusion to the
processor caches, as permitted by the implementation. It is IMPLEMENTATION DEFINED what levels of cache
and TLB are controlled by these requests, and it is IMPLEMENTATION DEFINED to what extent the intrusion
is limited.
The DBGDSCCR also provides a mechanism for a debugger to force writes to memory through to the point
of coherency without the overhead of issuing additional operations.
The DBGDSCCR and DBGDSMCR controls must apply for all memory operations issued in Debug state
when DBGDSCR.ADAdiscard, the Asynchronous Data Aborts Discarded bit, is set to 1. It is
IMPLEMENTATION DEFINED whether memory operations issued in Debug state whilst this bit is not set to 1
are affected by the DBGDSCCR and DBGDSMCR.
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