ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Performance Monitors
0x0B Instruction that writes to the CONTEXTIDR architecturally executed.
This counter does not increment for a conditional instruction that fails its condition code
check.
0x0C Software change of PC, except by an exception, architecturally executed.
This counter does not increment for a conditional instruction that fails its condition code
check.
0x0D Immediate branch architecturally executed:
B{L}
BLX
CB{N}Z ,
HB{L} #HandlerId (ThumbEE state only)
HB{L}P #, #HandlerId (ThumbEE state only).
This counter counts for all immediate branch instructions that are architecturally executed,
including conditional instructions that fail their condition code check.
0x0E Procedure return, other than exception return, architecturally executed:
BX R14
MOV PC,LR
POP {…,PC}
LDR PC,[SP],#offset
LDMIA R9!,{…,PC} (ThumbEE state only)
LDR PC,[R9],#offset (ThumbEE state only).
This counter does not increment for a conditional instruction that fails its condition code
check.
Note
Only these instructions are counted as procedure returns. For example, the following are not
counted as procedure return instructions:
BX R0 (Rm != R14)
MOV PC,R0 (Rm != R14)
LDM SP,{…,PC} (writeback not specified)
LDR PC,[SP,#offset] (wrong addressing mode).
0x0F Unaligned access architecturally executed. This counts each instruction that is an access to
an unaligned address. That is, the instruction either triggered an unaligned fault, or would
have done so if the CPSR.A bit had been 1.
This counter does not increment for a conditional instruction that fails its condition code
check.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C9-15