ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The System Level Programmers’ Model
B1.7 Coprocessors and system control
The ARM architecture supports sixteen coprocessors, usually referred to as CP0 to CP15. These
coprocessors are introduced in Coprocessor support on page A2-68. The architecture reserves two of these
coprocessors, CP14 and CP15, for configuration and control related to the architecture:
CP14 is reserved for the configuration and control of:
— debug features, see The CP14 debug register interfaces on page C6-32
— execution environment features, see Execution environment support on page B1-73.
CP15 is called the System Control coprocessor, and is reserved for the control and configuration of
the ARM processor system, including architecture and feature identification.
This section gives:
general information about the CP15 registers, in CP15 System Control coprocessor registers
information about access controls for coprocessors CP0 to CP13, in Access controls on CP0 to CP13
on page B1-63.
B1.7.1 CP15 System Control coprocessor registers
The implementation of the CP15 registers depends heavily on whether the ARMv7 implementation is:
an ARMv7-A implementation with a Virtual Memory System Architecture (VMSA)
an ARMv7-R implementation with a Protected Memory System Architecture (PMSA).
Therefore, detailed descriptions of the CP15 registers are given in:
CP15 registers for a VMSA implementation on page B3-64
CP15 registers for a PMSA implementation on page B4-22.
Registers that are common to VMSA and PMSA implementations are described in both of these sections.
Some registers are implemented differently in VMSA and PMSA implementations.
Those descriptions do not include the registers that implement the processor identification scheme, CPUID.
The CPUID registers are described in Chapter B5 The CPUID Identification Scheme.
CP15, the System Control coprocessor, can contain up to 16 primary registers, each of which is 32 bits long.
The CP15 register access instructions define the required primary register. Additional fields in the
instruction are used to refine the access, and increase the number of physical 32-bit registers in CP15. In
descriptions of the System Control coprocessor the 4-bit primary register number is used as a top level
register identifier, because it is the primary factor determining the function of the register. The 16 primary
registers in CP15 are identified as c0 to c15.
For details of register access rights and restrictions see the descriptions of the individual registers. In
ARMv7-A implementations, see also Effect of the Security Extensions on the CP15 registers on page B3-71.
The CP15 register access instructions are:
MCR, to write an ARM core register to a CP15 register, see MCR, MCR2 on page A8-186
MRC, to read the value of a CP15 register into an ARM core register, see MRC, MRC2 on page A8-202.
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