ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Register Interfaces
Meanings of terms and abbreviations used in this section
The following terms and abbreviations are used in the tables that summarize the access permissions:
X Don't care. The outcome does not depend on this condition.
0 The condition is false.
1 The condition is true. For more information, see Table C6-16.
IG/ABT The access is ignored or aborted.
Note
The IG/ABT response might be implemented outside the processor, for example, by the
system or DAP.
Proceed The access must not be ignored, but the processor or system might return an error response.
For more information about the response returned, see:
Permissions summary for separate debug and core power domains on page C6-48
Permissions summary for SinglePower (debug and core in single power domain) on
page C6-50.
Not possible When the debug logic is powered down, accessing the debug registers is not possible. The
system must respond to the access, and the response is IMPLEMENTATION DEFINED. ARM
recommends that the system returns an error response.
Error Error response. Writes are ignored and reads return an UNKNOWN value.
OK Read or write access succeeds. Writes to read-only locations are ignored. Reads from RAZ
or write-only locations return zero.
Some read/write registers include bits that are read-only. Unless otherwise stated in the bit
description, these bits ignore writes.
UNP The access has UNPREDICTABLE results. Reads return UNKNOWN value.
DBGLAR Lock Access Register, see Lock Access Register (DBGLAR) on page C10-94. This is one of
the management registers.
Table C6-16 lists the control conditions used in this section, and tells you where you can find more
information about each of these controls. These conditions can be given an argument of X, 0 or 1, as defined
at the start of this section. The table gives more information about the meaning when the argument is 1 for
each condition.
Table C6-16 Meaning of (Argument = 1) for the control condition
Control condition Meaning of (Argument = 1) For details see
Debug logic powered The debug power domain is powered up a Permissions in relation to power-down on
page C6-28
Core logic powered The core power domain is powered up a
Processor powered The single power domain is powered up a
Sticky power-down DBGPRSR[1] = 1
C6-46 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B