ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Protected Memory System Architecture (PMSA)
nU, bit [0] Not Unified MPU. Indicates whether the MPU implements a unified memory map:
nU == 0 Unified memory map. Bits [23:16] of the register are zero.
nU == 1 Separate Instruction and Data memory maps.
Accessing the MPUIR
To access the MPUIR you read the CP15 registers with set to 0, set to c0, set to c0, and
set to 4. For example:
MRC p15,0,,c0,c0,4 ; Read CP15 MPU Type Register
B4.6.10 c0, Multiprocessor Affinity Register (MPIDR)
The Multiprocessor Affinity Register, MPIDR, provides an additional processor identification mechanism
for scheduling purposes in a multiprocessor system. In a uniprocessor system ARM recommends that this
register returns a value of 0.
The MPIDR is:
a 32-bit read-only register
accessible only in privileged modes
introduced in ARMv7.
The format of the MPIDR is:
31 24 23 16 15 8 7 0
0 0 0 0 0 0 0 0 Affinity level 2 Affinity level 1 Affinity level 0
Note
In the MIDR bit definitions, a processor in the system can be a physical processor or a virtual processor.
Bits [31:24] Reserved, RAZ.
Affinity level 2, bits [23:16]
The least significant affinity level field, for this processor in the system.
Affinity level 1, bits [15:8]
The intermediate affinity level field, for this processor in the system.
Affinity level 0, bits [7:0]
The most significant level field, for this processor in the system.
In the system as a whole, for each of the affinity level fields, the assigned values must start at 0 and increase
monotonically.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B4-37