ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
MCR p15,0,,c7,c8,2 ; Write CP15 VA to User Read VA to PA Translation Register
MRC p15,0,,c7,c4,0 ; Read CP15 PA from Physical Address Register
An example of a VA to PA translation when the Security Extensions are implemented and the processor is
in the Secure state is:
MCR p15,0,,c7,c8,5 ; Write VA to Other State Privileged Write VA to PA Translation Register
; Performs VA to PA translation for Non-secure security state
MRC p15,0,,c7,c4,0 ; Read PA from Physical Address Register
VA to PA translation when the MMU is disabled
The VA to PA translation operations occur even when the MMU is disabled. The operations report the flat
address mapping and the MMU-disabled value of the attributes and permissions for the data side accesses.
These include any MMU-disabled re-mapping specified by the TEX-remap facilities. The SuperSection bit
is 0 when the MMU is disabled. For more information about the address and attributes returned when the
MMU is disabled see Enabling and disabling the MMU on page B3-5.
When the Security Extensions are implemented, this information applies when the MMU is disabled in the
security state for which the VA to PA translation is performed.
B3.12.33 CP15 c7, Miscellaneous functions
CP15 c7 provides a number of functions, summarized in Figure B3-10 on page B3-65. This section
describes only the CP15 c7 miscellaneous operations.
Figure B3-19 shows the CP15 c7 miscellaneous operations. It does not show the other CP15 c7 operations.
CRn opc1 CRm opc2
c7 0 c0 4
NOP, was Wait For Interrupt (CP15WFI) in ARMv6
c5 4
CP15ISB, Instruction Synchronization Barrier operation
c10 4
CP15DSB, Data Synchronization Barrier operation
5
CP15DMB, Data Memory Barrier operation
c13 1 NOP, was Prefetch instruction by MVA in ARMv6
Read-only Read/Write Write-only Bold text = Accessible in User mode
The CP15 c7 miscellaneous operations are described in:
CP15 c7, Data and Instruction Barrier operations on page B3-137
CP15 c7, No Operation (NOP) on page B3-138.
Figure B3-19 CP15 c7 Miscellaneous operations
B3-136 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B