ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Register Interfaces
accesses, that port might serialize accesses to the registers from the two interfaces. However, the effects of
reads and writes to these registers are such that the behavior observed from either interface appears as
UNPREDICTABLE.
Internal view External view
DBGDSCRint
DBGDSCR
DBGDSCRext
(Read-only)
RXfull_l
(Read/write)
1 (on writes)
DBGDTRTXint
(Write-only)
0 (on reads)
DBGDTRRXint
(Read-only)
Copied on reads
RXfull
TXfull_l
Copied on reads
TXfull
DBGDTRTX
DBGDTRRX
Figure C6-2 v7 Debug Internal (int) and External (ext) views of the DCC registers
Note
DBGDSCRint and DBGDSCRext only provide different views onto the underlying DBGDSCR
DBGDTRRXint and DBGDTRRXext only provide different views onto the underlying
DBGDTRRX Register
DBGDTRTXint and DBGDTRTXext only provide different views onto the underlying DBGDTRTX
Register.
See also:
Debug Status and Control Register (DBGDSCR) on page C10-10
Host to Target Data Transfer Register (DBGDTRRX) on page C10-40
Target to Host Data Transfer Register (DBGDTRTX) on page C10-43.
DBGDTRTXext
(Read/write)
DBGDTRRXext
(Read/write)
C6-22 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B
TX
Read
Logic
RX
Write
Logic