ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
VDUP. , Encoded as Q = 1
VDUP. , Encoded as Q = 0
where:
Instruction Details
See Standard assembler syntax fields on page A8-7. An ARM VDUP instruction must be
unconditional.
The data size for the elements of the destination vector. It must be one of:
8 encoded as [b,e] = 0b10
16 encoded as [b,e] = 0b01
32 encoded as [b,e] = 0b00.
The destination vector for a quadword operation.
The destination vector for a doubleword operation.
The ARM source register.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
scalar = R[t];
for r = 0 to regs-1
for e = 0 to elements-1
Elem[D[d+r],e,esize] = scalar;
Exceptions
Undefined Instruction.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-595