ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Register
number
33 0x084 Write-only v7 e Instruction Transfer Register (DBGITR) on
page C10-46.
Debug Register Interfaces
Read-only v7 e Program Counter Sampling Register (DBGPCSR) on
page C10-38.
34 0x088 Read/write v7 e DBGDSCR external view f. See Debug Status and
Control Register (DBGDSCR) on page C10-10.
35 0x08C Read/write v7 e DBGDTRTX external view f . See Target to Host Data
Transfer Register (DBGDTRTX) on page C10-43.
36 0x090 Write-only v7 only Debug Run Control Register (DBGDRCR), v7 Debug
only on page C10-29.
37-39 - - - Reserved.
40 0x0A0 Read-only v7 only Program Counter Sampling Register (DBGPCSR) on
page C10-38
41 0x0A4 Read-only v7 only Context ID Sampling Register (DBGCIDSR) on
page C10-39
42-63 - - - Reserved.
64-79 0x100-
0x13C
80-95 0x140-
0x17C
96-111 0x180-
0x1BC
112-127 0x1C0-
0x1FC
Read/write
or -
Read/write
or -
Read/write
or -
Read/write
or -
128-191 - - - Reserved.
Table C6-2 Debug register map (continued)
Offset Access a Versions b Name and reference to description
All Breakpoint Value Registers (DBGBVR) on page C10-48
or Reserved.
All Breakpoint Control Registers (DBGBCR) on
page C10-49 or Reserved.
All Watchpoint Value Registers (DBGWVR) on
page C10-60 or Reserved.
All Watchpoint Control Registers (DBGWCR) on
page C10-61 or Reserved.
192 0x300 Write-only v7 only OS Lock Access Register (DBGOSLAR) on
page C10-75.
193 0x304 Read-only v7 only OS Lock Status Register (DBGOSLSR) on page C10-76.
194 0x308 Read/write v7 only OS Save and Restore Register (DBGOSSRR) on
page C10-77.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C6-19