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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Instruction Details<br />

A8.6.17 BFC<br />

Bit Field Clear clears any number of adjacent bits at any position in a register, without affecting the other<br />

bits in the register.<br />

Encoding T1 <strong>ARM</strong>v6T2, <strong>ARM</strong>v7<br />

BFC ,#,#<br />

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

1 1 1 1 0 (0) 1 1 0 1 1 0 1 1 1 1 0 imm3 Rd imm2 (0) msb<br />

d = UInt(Rd); msbit = UInt(msb); lsbit = UInt(imm3:imm2);<br />

if BadReg(d) then UNPREDICTABLE;<br />

Encoding A1 <strong>ARM</strong>v6T2, <strong>ARM</strong>v7<br />

BFC ,#,#<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

cond 0 1 1 1 1 1 0 msb Rd lsb 0 0 1 1 1 1 1<br />

d = UInt(Rd); msbit = UInt(msb); lsbit = UInt(lsb);<br />

if d == 15 then UNPREDICTABLE;<br />

A8-46 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

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